Design Verification Engineer
The role involves ASIC and FPGA verification including contributing to verification methodology, developing test plans that ensure high coverage between random, directed and in-system environments, system infrastructure development and debug, with significant focus on testing infrastructure development.
Responsibilities may include:
- ASIC and FPGA verification in a System Verilog (OVM) and Verilog-based environment
- Architect and implement scalable, reusable test benches, fully inclusive of random environment, functional coverage, error generation, checkers and monitors, and assertion methodology based on OVL or SVA
- Tool creation, gate simulation, coverage analysis, integrating and testing standard IP models
- System-level contribution such as performance study, interaction with software, QA, and architecture team
Qualifications:
- Strong verification background and proven experience in architecting and implementing complex, reusable test benches
- Proficiency in object-oriented programming and data structures
- Proficiency in Verilog and System Verilog (or other HVL) required. Programming skill and experience in one or more of C, C++ and Perl is a strong plus. Comfort with a diversity of programming environments, tools, and challenges
- Experience with high speed serial interfaces (such as PCIe) or networking a strong plus
- Experience with silicon bring up
- Experience with industry standard methodologies such as OVM, VMM, AVM, and eRM
- Strong debug skills
- Candidate will likely have an MS in EE with 8 or more years of relevant experience
To apply for this position, send your resume to resume@seamicro.com with the corresponding job title.
