Careers

At SeaMicro we believe data centers can be vastly more power efficient than they are today. To this end, we have tremendous customer support and outstanding Venture Capital backing. Our staff is comprised of experts with decades of experience and we are always looking for exceptional people who can add to our strength.

SeaMicro is a rapidly growing technology pioneer so you will wear many hats and have opportunity to grow. We believe that working for SeaMicro will be the most exciting and challenging chapter of your career.

The following positions are currently open.

 

Senior Test Engineer / QA Engineer

Responsibilities:

Designing, automating and executing test plans for a complex datacenter appliance.

Qualifications:

• Excellent understanding of Ethernet and TCP/IP protocol suite.
• Strong understanding of ARP, DHCP, NAT, and DNS
• Experience in hardware platform testing  including Card Bringup and High Availability
• Experience in feature testing of switching protocols like VLAN, LACP, STP, RSTP, MSTP or PVST+
• Experience in using third party test equipment like IXIA, Smartbits
• Proficient in at least one scripting language (Perl, TCL, Python, Expect, etc) to automate test cases.
• Hands on experience on Cisco, Foundry, Force10 or  Juniper switches and routers.
• BE in CS/EE with 5 years of experience
• MS in CS/EE with 2-3 years of experience
• Familiarity with feature testing of routing protocols like OSPF, ISIS or BGP is a plus
• Familiarity with Multicast Protocols (IGMP, PIM-SM, MSDP) and MPLS a plus
• Experience in troubleshooting packet flow inside a switch/router is a plus
• Experience with testing IPv6 is a plus
• Cisco, Juniper certifications is a plus
• Linux System Admin experience is a plus

 

Senior Software Engineer – Embedded Management Plane

The position requires someone with knowledge of the architecture and detailed design of a management plane that services multiple northbound applications, including multiple, simultaneous CLI sessions, SNMP agents, as well as other applications.  The candidate has implemented scalable, flexible, management architectures that are distributed across multiple platforms and handles a common overlapping modules that service the various management clients efficiently.  
For SNMP, the candidate is familiar with the v1, v2c and v3 portions of the protocol.  The candidate is familiar with a multitude of general MIBs and can easily convert proprietary data sets into a well-structured enterprise MIB definition.  The candidate can also design and implement well-structured, straight-forward, general purpose MIB manipulation code.  For the CLI, the candidate understands the design of command tree structure definitions and parsing in text and XML formats.  For configuration data processing, the candidate understands simple database definition, creation, manipulations and propagation to the rest of the system during the boot sequence and for run-time updates.  The candidate also understands the challenges and overlaps of operational data (status, events, alerts and statistics) querying and processing.  
 Finally, it is highly desirable that the applicant be familiar with the agent side of an IPMI implementation as well as AAA implemented with TACACS+ and RADIUS.

Details:

• A senior embedded software engineer with strong design skills. The candidate should have been technical leads on multiple projects.
• Candidates should have 7+ years of industry experience writing production code that shipped with a product to external customers.  Their designs must include accounting for efficiency, performance and the processor platforms that are being used and must basic OOD concepts.  The candidates must also be familiar with code refactoring for stability and performance.
• Candidate must have very recent, substantial experience writing code in C on either a Linux or BSD platform.  They should be very comfortable with all aspects of C programming, including pointer manipulation and bitwise operations as well as writing code that includes the necessary levels of acceptable error handling.
• Candidate must have a history of implementing best practices in software development.  This includes taking full responsibility for thoroughly testing their own code without the assistance of others;  The front end of the process includes having a good understanding of the existing architecture and identifying and vetting functional requirements.
• Candidate should have  start-up experience so that they  understand the pace of start-ups
• A BS degree in either EE, CS or Computer Engineering.

Senior Hardware Design Engineer

SeaMicro is looking for an experienced Senior Hardware Design Engineer to architect and implement a flexible and scalable networking solution for its next generation data center products. This is an excellent opportunity for high-energy candidates who can take a complex networking solution from conception, through execution, to first customer shipment.

Responsibilities:

• Work with a team of hardware and software engineers to define the high-level architecture
• Drive micro-architecture definition, RTL development, and system bring up
• Interface with external vendors as well as other teams within SeaMicro including software development, systems engineering, and product marketing

  Skills:

• 7+ yrs of experience in high-performance/high-bandwidth micro-architecture
• 7+ yrs experience in Verilog RTL development, with some experience in design/development of Networking chips
• iExperience with designs based on network processors, 10G interfaces, and DDR memory controllers desirable
• Solid understanding of L2 Ethernet switching protocols including VLAN, Broadcast/Multicast, and LACP is a plus
• Working knowledge of IPv4, IPv6, ACLs, and QOS
• Experience with ASIC and FPGA implementation flows is a plus
• Strong problem solving and debugging skills
• Experience with product bring up
• Excellent communication skills
• Candidate will likely have an MS EE/CS with 8+ years of experience

Systems (HW) engineering position

Responsibilities

• Review PCA requirements
• Develop functional specification for PCAs
• Design and develop schematics for PCAs
• Work with software engineering in functional specification development
• Oversee PCB design/layout, including stack-up, traces, routing, design for manufacturability and test
• Bring up and debug PCAs
• Bring multiple PCB designs to production, including EDVT, EMI, root cause analysis of problems
• Work at System level to improve efficiencies & reduce overall cost (architecture, BOM, Layer counts)
• Feasibility analysis for future designs including analysis of Power delivery and Signal Integrity
• Work with outside suppliers and Contract Manufacturers

  Skills

• Candidate will likely have MS in EE or equivalent with 10 or more years of related hardware design experience
• Experience and familiarity with schematic capture, and PCB layout tools
• 3+ years experience with high speed serial designs including XAUI and PCI-E
• Experience with circuit simulation tools (SPICE), and Signal / Power Integrity concerns and analysis
• Able to design logic for CPLDs and small FPGAs
• Experience in designing server systems & dealing with large system design issues desired
• Experience with POL, or SMPS design
• Good oral and written communications skills

Design Verification Lead Engineer

The role involves ASIC and FPGA verification including developing a verification methodology, test plan that ensures high coverage between random, directed and in-system environments, system infrastructure development and debug, with significant focus on testing infrastructure development.

Responsibilities may include

• ASIC and FPGA verification in a System Verilog and Verilog based environment
• Architect and implement Test Bench, fully inclusive of random environment, error generation, checkers and monitors, assertion methodology based on OVL
• Responsible for Gate Simulation methodology, Coverage Analysis, integrating and testing standard IP models

  Required skills include

• Strong verification background and proven experience in architecting and implementing comprehensive test benches
• Strong programming skills in Verilog and System Verilog required. Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments, tools and challenges
• Knowledge of PCI Express and high speed PHYs
• Experience with Silicon bring up.
• Strong debug skills
• Candidate will likely have MS in EE with 8 or more years of relevant experience

To apply please email your resume and cover letter to resume@seamicro.com